Paper Key : IRJ************735
Author: Daljeet Kaur Khanduja
Date Published: 31 Oct 2023
Abstract
The design and implementation of FIR filter banks for multirate analysis and synthesis are examined in this paper using a least-Pth norm approach and floating-point arithmetic. However, in order to minimize cost and energy, they are typically implemented using fixed-point arithmetic. This paper discusses the conversion of floating points to fixed points for software implementation while taking the filter structure into consideration. Our strategy aims to identify the fixed-point specification that reduces the amount of time required to execute code for a given accuracy requirement. In our approach, the processor architecture is considered, and the code generation process is integrated with the floating-point to fixed-point conversion process. The arithmetic complexity is then decreased while still adhering to design restrictions by employing various realization structures. The current work aims to reduce the number of memory accesses while boosting the speed of filter computation. As a result, the system's processing speed and space utilization time have both decreased. The effectiveness of two different filter architectures is evaluated and compared. A signal to noise ratio (SNR) of between 50 and 60 dB is observed from a variety of signal samples, which is suitable for signal analysis and synthesis purposes.
DOI LINK : 10.56726/IRJMETS45534 https://www.doi.org/10.56726/IRJMETS45534