Paper Key : IRJ************283
Author: Alpana Nekhar,Divyanshu Rao,Ravi Mohan
Date Published: 05 Apr 2025
Abstract
The arithmetic and Logic Unit (ALU) is the most crucial and core component of the central processing unit as well as of several embedded systems and microprocessors. ALU consists of many computational units like adders, multipliers, logical units etc. Vedic Mathematics concepts are proposed here for designing the computational units of an 8-bit ALU. Here, a high-speed 88bit multiplier is proposed which is based on the Vedic multiplier mechanism. A divider based on Vedic mathematics is also proposed here. The proposed Vedic mathematics-based ALU is designed using high-level hardware description language Verilog, followed by synthesisation using the EDA tool, Xilinx ISE 14.1. Finally, the synthesized circuit has been implemented on Xilinx Spartan-6 Field Programmable Gate Array (FPGA) device.